- Locations: California, Texas, Maryland, Massachusetts, Minnesota
- DFT ASIC Engineer
- Alchemy Search Partners (San Jose, CA)
- ...Depth Knowledge: DFT techniques including Memory Bist and Repair, Scan, Compression, Logic Bist, PLL, Serdes test using state of the art EDA tools (Synopsys, Mentor , LogicVison, Syntest). Knowledge of tcl scripting language, Magma synthesis tool. Experience Desired: Requirements: minimum...
- SOC Architect
- Terran Systems (San Jose, CA)
- ...This position is responsible for technically leading a group of engineers to design to the specifications of state-of-the- art optical network ASIC . Duties include managing project schedule and resource management, hands-on system architect or chip-level micro-architect, RTL design,...
- ASIC Design and Verification Engineer
- QLogic (Shakopee, MN)
- ASIC Design and Verification Engineer Tracking Code 3390 Job Description QLogic simplifies the process of networking...success. All tasks are completed in a team environment using state of the art simulation and analysis tools. Required Skills * Bachelors or Masters in Electrical...
- Engineer, Staff ASIC Design
- Marvell (Santa Clara, CA)
- ...Qualifications: Looking for the candidate who is familiar with digital IC design methodologies, understands all stages of ASIC design flows, and is experienced with state-of-the- art design tools. The candidate is strong in logic design and verification, and has solid knowledge of...
- Engineer, Senior ASIC Design
- Marvell (Santa Clara, CA)
- ...Qualifications: Looking for the candidate who is familiar with digital IC design methodologies, understands all stages of ASIC design flows, and is experienced with state-of-the- art design tools. The candidate is strong in logic design and verification, and has solid knowledge of...
- ASIC /Physical Design Engineer - Senior Levels
- Qualcomm (San Diego, CA)
- Requisition # G1858361 Job Title ASIC /Physical Design Engineer - Senior Levels Post Date 10/30/2009 Division...engineers to implement complex SOC designs for wireless applications in state-of-the- art VDSM technologies using the latest EDA tools and methodologies....
- Senior ASIC Design Engineer - CMOS Image Sensors (location: Irvine, California)
- TFI (San Jose, CA)
- Senior ASIC Design Engineer - CMOS Image Sensors (location: Irvine, California), Senior ASIC Design...closely with experienced design and system engineering teams using state of the art technologies to develop CMOS image sensors and SOC solutions for mobile consumer...
- Engineer, Staff ASIC Design
- Marvell Semiconductor, Inc. (Santa Clara, CA)
- ...Qualifications: Looking for the candidate who is familiar with digital IC design methodologies, understands all stages of ASIC design flows, and is experienced with state-of-the- art design tools. The candidate is strong in logic design and verification, and has solid knowledge of...
- Engineer, ASIC Design
- Marvell (Santa Clara, CA)
- Job Title: Engineer, ASIC Design Job Category: Engineering Job Sub Category: Digital Design Qualifications: Education preferred:.... IP integration and SOC flow Description: . Design and verify state-of-the- art highly integrated storage SOCs for desktop and notebook storage systems and...
- Principal Engineer ASIC
- Boston Scientific (Valencia, CA)
- Principal Engineer ASIC Requisition ID 31624 Full/Part Time x Location Valencia CA Description Purpose/Role Statement...design experience. Ability to understand & design with state of the art electronic devices. Experience in the application of various analysis of, design...
- ASIC /FPGA Rtl Engineer
- R Systems (Roseville, CA)
- ...FPGAs from Altera, Lattice and/or XilinxExperience with one or more of the following technology areas:Storage area networking protocolsState-of-the- art volatile and non-volatile memoryEmbedded processors and embedded processor peripheralsAble to write clean, readable, and maintainable code...
- DFT ASIC Engineer
- Alchemy Search Partners (San Jose, CA)
- ...Depth Knowledge: DFT techniques including Memory Bist and Repair, Scan, Compression, Logic Bist, PLL, Serdes test using state of the art EDA tools (Synopsys, Mentor , LogicVison, Syntest). Knowledge of tcl scripting language, Magma synthesis tool. Experience Desired: Requirements: minimum...
- SOC Architect
- Unknown (San Jose, CA)
- ...position is responsible for technically leading a group of engineers to design to the specifications of state-of-the- art optical network ASIC . Duties include managing project schedule and resource management, hands-on system architect or chip-level micro-architect, RTL design,...
- ASIC /FPGA Rtl Engineer
- R Systems (Roseville, CA)
- ...FPGAs from Altera, Lattice and/or XilinxExperience with one or more of the following technology areas:Storage area networking protocolsState-of-the- art volatile and non-volatile memoryEmbedded processors and embedded processor peripheralsAble to write clean, readable, and maintainable code...