- Locations: California, Pennsylvania, Colorado, Texas, Idaho
- Related Keywords: ASIC, ASIC SOC, Design, Physical, Physical Design, SOC, SOC Physical Design
- Read Channel Design Implementation Engineer
- LSI Logic Corporation (Allentown, PA)
- ...Design Implementation Engineer Storage Products Minimum Requirements: Experience/exposure to physical design and timing closure required. Focus in the...The candidate will work on leading edge storage solutions in ASIC , full custom and SoC environments. The ideal candidate...
- Analog Design Engineer
- ON Semiconductor (Austin, TX)
- As an Analog Design Engineer in the Corporate R&D group, you will:Focus on PLL,...high-level description languages. Create required digital/analog models required for digital SOC designs.Create IP characterization plans and automated test programs.Perform silicon validation...
- ASIC / Physical Design Engineer - Senior Levels
- Qualcomm (San Diego, CA)
- Requisition # G1858361 Job Title ASIC / Physical Design Engineer - Senior Levels Post Date 10/30/2009...increasingly sophisticated wireless community. Opportunities for exceptional IC physical design engineers to implement complex SOC designs for wireless applications...
- Engineer, Senior Staff ASIC Design
- Marvell (Boise, ID)
- ... Qualifications: Thorough understanding of CMOS design . Expert in backend ASIC design flow and physical design ... design . Experience in place-and-route and RC extraction. Experience with physical design tools and scripting ( SOC Encounter, Primetime,...
- Director/Principal Engineer - SOC Integration
- Qualcomm (San Diego, CA)
- Requisition # E1844841 Job Title Director/Principal Engineer - SOC Integration Post Date 9/25/2009 Division QCT Job Area Engineering - Hardware...Close interaction with all ASIC development groups (front end, physical design , technology and product engineering) is key, to...
- ASIC Design And Verification Engineer
- Terran Systems (San Jose, CA)
- ASIC Verification Requirements: Position OverviewProspective candidate will design verification of a high performance physical layer SoC . Position Responsibilities- Prospective candidate will be responsible for contributing to the development of overall verification strategy,...
- ASIC Design And Verification Engineer
- Unknown (San Jose, CA)
- ASIC DESIGN AND VERIFICATION ENGINEERASIC Verification Requirements:Position OverviewProspective candidate will design verification of a high performance physical layer SoC .Position Responsibilities- Prospective candidate will be responsible for contributing to the...
- ASIC Design And Verification Engineer
- Terran Systems (San Jose, CA)
- ASIC Verification Requirements: Position Overview Prospective candidate will design verification of a high performance physical layer SoC . Position Responsibilities - Prospective candidate will be responsible for contributing to the development of overall verification strategy,...
- Senior ASIC Design Engineer
- Broadcom Corporation (Irvine, CA)
- ...designers from around the world as well as working with physical designers, simulation/environment teams, and DFT teams to integrate into...Requirements : Job Requirements: Minimum 3-7 years of complex/high performance SOC design experience Excellent communication skills as job...
- SOC Architect
- Unknown (San Jose, CA)
- SOC ArchitectJob Title: Senior ASIC EngineerSummary:We're a company focused on providing Silicon...and static timing analysis, using Synopsys' products or equivalent. Works with internal ASIC physical design team for layout and final chip tape-outs. Provide...
- SOC Architect
- Terran Systems (San Jose, CA)
- ...and hands-on RTL design using Verilog, synthesis and static timing analysis, using Synopsys' products or equivalent. Works with internal ASIC physical design team for layout and final chip tape-outs. Provide Technical Guidance for Team Members Required Skills and Experience:...
- Physical Design and VLSI CAD Design
- Inmata Solutions (San Jose, CA)
- Asic Physical Design Engineer : Responsibilities and Duties This position will be responsible for ...clocking integrity, and signal integrity analysis ? DRC/LVS Qualifications ? Hands-on experience in physical design of large SoC ?s ? Extensive experience in...
- SOC Architect
- Terran Systems (San Jose, CA)
- ...and hands-on RTL design using Verilog, synthesis and static timing analysis, using Synopsys' products or equivalent. Works with internal ASIC physical design team for layout and final chip tape-outs. Provide Technical Guidance for Team Members Required Skills and Experience:...
- SOC Architect
- Unknown (San Jose, CA)
- SOC ArchitectJob Title: Senior ASIC EngineerSummary:We're a company focused on providing Silicon...and static timing analysis, using Synopsys' products or equivalent. Works with internal ASIC physical design team for layout and final chip tape-outs. Provide...