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ASIC Verification Sr. Staff: Conexant (Waltham, MA); ...Verilog and C++ (or Object Oriented Verification languages such as Vera, Specman or System Verilog) required. Experience with OVM/VVM, Verilog Assertions, Functional...; Email this job
techcareers.com (03/07/10)
Sr Sales Technical Leader: Cadence Design Systems, Inc. (San Diego, CA); ...in creating Coverage Driven Verification environments utilizing e-language tools [ SpecMan ], Vera, SystemVerilog or SystemC/C++ is required. Track record of...; Email this job View duplicates
KODA.us (02/06/10)

ASIC Verification Engineer: Intel (Austin, TX); ...computing functionality at 10/40Gb speeds. These testbenches are implemented using the Specman `e' language. As part of the pre-silicon Architectural Validation (AV)...; Email this job
Intel (03/11/10)
Engineer, Design Verification Test (DVT): Marvell (Austin, TX); ...extensively used at least one of the following verification methodologies: C++/System Verilog/Vera/ Specman E language; and at least one of the following simulator...; Email this job
Marvell (03/13/10)
Technical Leader , Advanced Verification Technologies: Cadence Design (San Diego, CA); ...in creating Coverage Driven Verification environments utilizing e-language tools [ SpecMan ], Vera, SystemVerilog or SystemC/C++ is required. Track record of...; Email this job
Climber.com (01/23/10)
Sales Technical Leader , Advanced Verification Technologies: Cadence Design Systems, Inc. (San Jose, CA); ...in creating Coverage Driven Verification environments utilizing e-language tools [ SpecMan ], Vera, SystemVerilog or SystemC/C++ is required. Track record of...; Email this job View duplicates
KODA.us (02/17/10)
Verification Engineers: Koa Networks (San Jose, CA); Verification Engineers Skills: programming skills SystemVerilog Vera Specman computer architecture PCIe Hypertransport USB2 ASIC Job Description: Candidate will work...; Email this job
Climber.com (03/18/10)
Design Verification Engineer: Spherion (Houston, TX); ...an approximately 6 month contract. Responsibilities: Test planning, test writing ( Specman /VHDL), debug, documentation, test bench creation, and working with the...; Email this job
AMightyRiver.com (03/18/10)
ASIC Design verification engineer: Resources Guru (San Jose, CA); Asic verification engineer-7+ yrs of experience working knowledge of Specman and Interlaken please send your resume at ###@resourcesguru.com feel free to call us...; Email this job
Dice.com (12/22/09)
ASIC Verification Engineer: Kutir Inc (Minneapolis, MN); ...constrained random verification tools such as System C, SystemVerilog, Vera or SpecMan . Please email your resume with hourly rate, availability, visa status and...; Email this job
Dice.com (01/06/10)
Verification Engineers: Koa Networks (San Jose, CA); Verification Engineers Skills: programming skills SystemVerilog Vera Specman computer architecture PCIe Hypertransport USB2 ASIC Job Description: Candidate will work...; Email this job
HotJobs (03/17/10)
Hardware Engineer: AlphaSoft Services (San Jose, CA); ...a contractor with the following skills: - Must have extensive experience with Specman Verification tool from Cadence - Experience with Interlaken (High speed version...; Email this job
Dice.com (12/22/09)