- Locations: California, Arizona, North Carolina, Minnesota, Massachusetts
- Related Keywords: ASIC, ASIC Physical, Physical, Synopsys
- Member of Technical Staff, ASIC Design
- GDA Technologies Inc (San Jose, CA)
- ...automating scripts. Bachelor's or equiv foreign degree in EE or Comp Eng Requires setup & execution of complete ASIC physical design flow using - Synopsys , - Cadence, & - Magma tools Fullchip assembly & tapeout to foundry; PERL, TCL, & TK scripting languages.
- SOC Architect
- Terran Systems (San Jose, CA)
- ...hands-on RTL design using Verilog, synthesis and static timing analysis, using Synopsys ' products or equivalent. Works with internal ASIC physical design team for layout and final chip tape-outs. Provide Technical Guidance for Team Members Required Skills and Experience: BSEE/MSEE...
- Analog and Mixed Signal ASIC Physical Design Engineer
- Static Control Components, Inc. (Sanford, NC)
- ...Inc. has an immediate opening for an Analog and Mixed Signal ASIC Physical Design Engineer. Responsibilities: As a member of the...aid of the marquee backend software from EDA companies like Mentor, Synopsys , etc. Major responsibilities will include, but not limited to: * Layout...
- ASIC / Physical Design Engineer - Senior Levels
- Qualcomm (San Diego, CA)
- Requisition # G1858361 Job Title ASIC / Physical Design Engineer - Senior Levels Post Date 10/30/2009 Division Qualcomm...participated in implementation of SOC designs in DSM technologies using latest Synopsys , Cadence and/or Magma PD toolsets. Technical depth in the areas of...
- Member of Technical Staff, ASIC Design
- GDA Technologies Inc (San Jose, CA)
- ...automating scripts. Bachelor's or equiv foreign degree in EE or Comp Eng Requires setup & execution of complete ASIC physical design flow using - Synopsys , - Cadence, & - Magma tools Fullchip assembly & tapeout to foundry; PERL, TCL, & TK scripting languages.
- Senior ASIC Design Engineer
- Broadcom Corporation (Irvine, CA)
- ...skills are a necessity as the candidate will be interfacing with multiple IP designers from around the world as well as working with physical designers, simulation/environment teams, and DFT teams to integrate into a chip level Verilog which will be used to derive the final product....
- Staff Physical Design Engineer
- LSI Logic Corporation (Mendota Heights, MN)
- ...working with LSI internal design groups providing technical applications support for customer ASIC program in the areas of physical planning, physical design, physical implementation, and physical verification. Experience with Synopsys ' IC Compiler required. This is a...
- Physical Design CAD Engineer
- Qualcomm (San Diego, CA)
- ...Include: . Work with design to identify areas for flow improvement, develop plans and implement improvements . Support ASIC physical design tools such as Synopsys ICC, Magma Talus and Cadence FE . Provide tool support and issue debugging services to design teams . Develop and...
- SOC Architect
- Unknown (San Jose, CA)
- ...RTL design using Verilog, synthesis and static timing analysis, using Synopsys ' products or equivalent. Works with internal ASIC physical design team for layout and final chip tape-outs. Provide Technical Guidance for Team MembersRequired Skills and Experience:BSEE/MSEE or...
- SOC Architect
- Terran Systems (San Jose, CA)
- ...hands-on RTL design using Verilog, synthesis and static timing analysis, using Synopsys ' products or equivalent. Works with internal ASIC physical design team for layout and final chip tape-outs. Provide Technical Guidance for Team Members Required Skills and Experience: BSEE/MSEE...
- Engineer, Staff Physical Design
- Marvell (Santa Clara, CA)
- ...design strategies, methodologies and deep sub-micron technology issues. Familiar with ASIC design flow, Verilog HDL, synthesis and timing closure. ?...communication skills. ? Must be a power user of either Synopsys suite (Astro, Apollo, JupiterXT, Physical Compiler, IC...
- Physical Design and VLSI CAD Design
- Inmata Solutions (San Jose, CA)
- Asic Physical Design Engineer : Responsibilities and Duties This position will be responsible for physical design...communication skills ? 5+ years physical design experience with 3+ Year experience in Synopsys and/or Magma physical design tool suites ? BSEE required,
- SOC Architect
- Unknown (San Jose, CA)
- ...RTL design using Verilog, synthesis and static timing analysis, using Synopsys ' products or equivalent. Works with internal ASIC physical design team for layout and final chip tape-outs. Provide Technical Guidance for Team MembersRequired Skills and Experience:BSEE/MSEE or...
- Senior ASIC Design Engineer
- Broadcom Corporation (Irvine, CA)
- ...skills are a necessity as the candidate will be interfacing with multiple IP designers from around the world as well as working with physical designers, simulation/environment teams, and DFT teams to integrate into a chip level Verilog which will be used to derive the final product....