Sponsored

Digital IC Design Engineer
Huawei USA (Plano, TX)
...with simulation and synthesis EDA tools. Specifically: Cadence NC-Sim (or Synopsys VCS, Mentor ModelSim), Synopsys DC, and Synopsys...with tools for simulating and debugging mixed signal ICs; including SPICE and fast SPICE simulators. Cadence AMS-Designer, UltraSim, and...
Jobirn.com (09/06/09)
 
Sr. Physical Design Methodology Engineer
NVIDIA Corporation (Santa Clara, CA)
...correlation, xtalk analysis, place and route. - Working knowledge of deep sub-micron issues. - Circuit level comprehension of time critical paths. Spice experience a plus. - Should have prior usage experience with P&R and timing analysis CAD tools from Magam (Talus/Blast/Quartz), ...
Climber.com (11/12/09)
 
Senior Circuit Design Engineer - Standard Cell
Broadcom (Tempe, AZ)
...of experience or an equivalent experience of over 15 years. Skills include Circuit design, place & route, Calibre, Hercules, Verilog/VHDL, Synopsys , spice simulation, verification, Cadence layout, Cadence schematic capture, Cadence skill language, Unix based scripting (perl,awk)
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Broadcom (11/19/09)
 
Senior Circuit Design Engineer - Standard Cell
Broadcom (Tempe, AZ)
...or an equivalent experience of over 15 years. Skills include Circuit design, place & route, Calibre, Hercules, Verilog/VHDL, Synopsys , spice simulation, verification, Cadence layout, Cadence schematic capture, Cadence skill language, Unix based scripting (perl,awk) Location:United...
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Climber.com (11/22/09)
 
Electrical/Hardware Engineer V
Hewlett Packard / HP (San Diego, CA)
...communications and transmission technologies Experience in wireless technologies, USB, PCIe, power supply design Familiarity & experience with Synopsys , Verilog, SPICE , ASIC design methodologies, & RISC processor architectures Additional Information: Travel Percentage: 25%
iHispano.com (10/09/09)
 
Digital IC Design Engineer
Huawei USA (Plano, TX)
...with simulation and synthesis EDA tools. Specifically: Cadence NC-Sim (or Synopsys VCS, Mentor ModelSim), Synopsys DC, and Synopsys...with tools for simulating and debugging mixed signal ICs; including SPICE and fast SPICE simulators. Cadence AMS-Designer, UltraSim, and...
Jobirn.com (09/06/09)
 
Engineer, Design Verification Test (DVT)
Marvell (Santa Clara, CA)
...and behaviorla modeling. Working knowledge of Verilog, Verilog AMS Synopsys DC-Compiler, Primetime, Matlab, C, System C, PLI and...PERL. Working knowledge of Verilog XL, NC-Verilog or VCS, SPICE and HSIM. Read channel and data storage experience/background...
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Marvell (08/31/09)
 
Sr. Physical Design Methodology Engineer
Nvidia (Santa Clara, CA)
...sub-micron issues. - Circuit level comprehension of time critical paths. Spice experience a plus. - Should be a power user...P&R and timing analysis CAD tools from Magma (Blast, Talus), Synopsys (Astro/PC/DC/PT/STAR-RC), Cadence (SOCE), Sequence (CoolPower) or Mentor Graphics. -...
Nvidia (09/02/09)
 
Sr. Physical Design Engineer
Nvidia (Austin, TX)
...- Working knowledge of deep sub-micron routing issues as they relate to power and timing. - Circuit level comprehension of time critical paths. Spice experience a plus. - Should be a power user of P&R and timing analysis CAD tools from Magma (Talus/Blast/Quartz), Synopsys ...
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Nvidia (10/08/09)
 
Sr. Physical Design Methodology Engineer
Nvidia (Santa Clara, CA)
...correlation, xtalk analysis, place and route. - Working knowledge of deep sub-micron issues. - Circuit level comprehension of time critical paths. Spice experience a plus. - Should have prior usage experience with P&R and timing analysis CAD tools from Magam (Talus/Blast/Quartz), ...
Nvidia (10/08/09)
 
Sr. Physical Design Methodology Engineer
NVIDIA Corporation (Santa Clara, CA)
...correlation, xtalk analysis, place and route. - Working knowledge of deep sub-micron issues. - Circuit level comprehension of time critical paths. Spice experience a plus. - Should have prior usage experience with P&R and timing analysis CAD tools from Magam (Talus/Blast/Quartz), ...
Climber.com (11/12/09)
 
Sr. Physical Design Methodology Engineer
NVIDIA Corporation (Santa Clara, CA)
...issues. - Circuit level comprehension of time critical paths. Spice experience a plus. - Should be a power user...and timing analysis CAD tools from Magma (Blast, Talus), Synopsys (Astro/PC/DC/PT/STAR-RC), Cadence (SOCE), Sequence (CoolPower) or Mentor Graphics.- Proficiency...
Climber.com (11/15/09)
 

Sponsored

Sr. Physical Design Methodology Engineer
NVIDIA Corporation (Santa Clara, CA)
...issues. - Circuit level comprehension of time critical paths. Spice experience a plus. - Should be a power user...and timing analysis CAD tools from Magma (Blast, Talus), Synopsys (Astro/PC/DC/PT/STAR-RC), Cadence (SOCE), Sequence (CoolPower) or Mentor Graphics.- Proficiency...
Climber.com (11/15/09)
 
Senior Circuit Design Engineer - Standard Cell
Broadcom (Irvine, CA)
...or an equivalent experience of over 15 years. Skills include Circuit design, place & route, Calibre, Hercules, Verilog/VHDL, Synopsys , spice simulation, verification, Cadence layout, Cadence schematic capture, Cadence skill language, Unix based scripting (perl,awk) Location:United...
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Climber.com (11/22/09)
 




 

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