- Locations: California, Arizona, Texas, Maryland, Minnesota
- Related Keywords: Synopsys, Verification
- Mask Design and Verification
- Unknown (Dallas, TX)
- ...with high-speed analog layout and device matching. TECHNICAL SKILLSInclude: Familiarity with the following tools may be required:Cadence schematic capture and layout tools;Cadence/Mentor/ Synopsys LVS/DRC verification tools.Must have strong schematic-to-layout translation skills.
- Member of Technical Staff, ASIC Design
- GDA Technologies Inc (San Jose, CA)
- ...customer requirements) ASIC backend physical design; ASIC backend physical verification & DFM (design for manufacturability) ASIC fullchip assembly Writing...execution of complete ASIC physical design flow using - Synopsys , - Cadence, & - Magma tools Fullchip assembly &...
- New Grad - ASIC Design Verification
- ViaSat (Cleveland, OH)
- ...reliable products Experience/Skills Required 1. Masters in Electrical Engineering 2. Educational focus on ASIC Design and ASIC Design Verification 3. Experience with Synopsys Design and Verification Tools 4. Demonstrated ability to design and develop in Verilog 5. Demonstrated...
- Mask Design and Verification
- Everest Consultants Inc (Dallas, TX)
- ...with high-speed analog layout and device matching. TECHNICAL SKILLS Include: Familiarity with the following tools may be required: Cadence schematic capture and layout tools; Cadence/Mentor/ Synopsys LVS/DRC verification tools. Must have strong schematic-to-layout translation skills.
- Physical Design Verification Engineer
- Sun Microsystems (Austin, TX)
- ...* Excellent communication and interpersonal skills. Preferred Knowledge : * Mentor DFM tool suite (CAA, LPC, VCMP). * Synopsys Hercules physical verification suite, PrimeYield tool suite. * Cadence Physical Verification System and SKILL programming language. Education and...
- Mask Design and Verification
- Charter Global Inc (Dallas, GA)
- ...Skills Include:* Familiarity with the following tools may be required:* Cadence schematic capture and layout tools;* Cadence/Mentor/ Synopsys LVS/DRC verification tools* Must have strong schematic-to-layout translation skillsPlease provide the following information:Candidate Full...
- Mask Design and Verification
- Unknown (Dallas, TX)
- ...with high-speed analog layout and device matching. TECHNICAL SKILLSInclude: Familiarity with the following tools may be required:Cadence schematic capture and layout tools;Cadence/Mentor/ Synopsys LVS/DRC verification tools.Must have strong schematic-to-layout translation skills.
- Physical Design Verification Engineer
- Sun Microsystems (Austin, TX)
- ...processes and excellent communication and interpersonal skills. Preferred Knowledge in Mentor DFM tool suite (CAA, LPC, VCMP), Synopsys Hercules physical verification suite, PrimeYield tool suite and Cadence Physical Verification System and SKILL programming language. Education and...
- Physical Design Verification Engineer
- Sun Microsystems (Santa Clara, CA)
- ...fabrication processes. * Excellent communication and interpersonal skills. Preferred Knowledge : * Mentor DFM tool suite (CAA, LPC, VCMP). * Synopsys Hercules physical verification suite, PrimeYield tool suite. * Cadence Physical Verification System and SKILL programming language.
- Senior Circuit Design Engineer - Standard Cell
- Broadcom (Tempe, AZ)
- ...of experience or an equivalent experience of over 15 years. Skills include Circuit design, place & route, Calibre, Hercules, Verilog/VHDL, Synopsys , spice simulation, verification , Cadence layout, Cadence schematic capture, Cadence skill language, Unix based scripting (perl,awk)
- Senior Circuit Design Engineer - Standard Cell
- Broadcom (Tempe, AZ)
- ...or an equivalent experience of over 15 years. Skills include Circuit design, place & route, Calibre, Hercules, Verilog/VHDL, Synopsys , spice simulation, verification , Cadence layout, Cadence schematic capture, Cadence skill language, Unix based scripting (perl,awk) Location:United...
- Staff Physical Design Engineer
- LSI Logic Corporation (Mendota Heights, MN)
- ...support for customer ASIC program in the areas of physical planning, physical design, physical implementation, and physical verification . Experience with Synopsys ' IC Compiler required. This is a position for developing and honing verbal and written communication skills, and...
- Mask Design and Verification
- Charter Global Inc (Dallas, GA)
- ...Skills Include:* Familiarity with the following tools may be required:* Cadence schematic capture and layout tools;* Cadence/Mentor/ Synopsys LVS/DRC verification tools* Must have strong schematic-to-layout translation skillsPlease provide the following information:Candidate Full...
- CAD Manager
- Unknown (Mountain View, CA)
- ...CAD tools Cadence Custom IC design products Mentor Graphics Back-end verification tools Maintain and develop Process Design Kit and cell libraries...P & R tools Familiar with Cadence, Mentor Graphics, Agilent, Synopsys Tools Required Experience: Minimum 5 years in a similar CAD...