- Locations: California, Minnesota, Texas, New York, Massachusetts
- Related Keywords: Vera, Vera Verification Engineer, Verification, Verification Vera ASIC
- Design Verification Engineers
- New NYC Opportunity! (New York, NY)
- ...achieved first-pass silicon success, and system-level verification . ~Proficiency with C, C++. ~ Must have experience with verification test languages such as Vera . Knowledge of VHDL or Verilog language and using synthesis tools is desired. ~Implement the verification strategy...
- Chip Verification Lead
- GDA Technologies Inc (San Jose, CA)
- Perform chip verification (including development of methodologies, test plans, compliance test suite, test bench creation, & test cases) using System Verilog, SystemC, C++, & VERA ; Develop scripts; Develop test bench components (like BFM, transactors, assertions, coverage,...
- Verification Engineer
- Fusion408 (Santa Clara, CA)
- ...C/C++, PERL, PLI is desirable - Familiarity with DSP & PHY layer communication protocols of 802.3 - Experience with Verilog, Vera verification environment, common RTL simulation & verification tools - System level & block level verification - Understanding...
- ASIC Design And Verification Engineer
- Unknown (San Jose, CA)
- ...languages: C/C++, PERL, PLI is desirable- Familiarity with DSP & PHY layer communication protocols of 802.3- Experience with Verilog, Vera verification environment, common RTL simulation & verification tools- System level & block level verification - Understanding of...
- ASIC Design And Verification Engineer
- Terran Systems (San Jose, CA)
- ...languages: C/C++, PERL, PLI is desirable- Familiarity with DSP & PHY layer communication protocols of 802.3- Experience with Verilog, Vera verification environment, common RTL simulation & verification tools- System level & block level verification - Understanding of...
- EDA Verification Engineer, Senior
- Qualcomm (San Diego, CA)
- ...communicate, coordinate and educate Skills/Experience . Prefer two to four years experience in CAD verification and/or ASIC verification . . Strong knowledge of HVLs( VERA ), HDLs(Verilog/VHDL/SystemVerilog), C/C++/SystemC. RTL simulation (ModelSim, VCS, Vera ), Formal ...
- Director/Principal Engineer of Design Verification and Validation - Wireless Communications
- Qualcomm (San Diego, CA)
- ...finish?strong track record on execution. Wireless system design or architecture experience and knowledge required. Experience with directed random verification in SystemVerilog, Vera , Verisity/Specman and/or SystemC preferred. You should have experience leading dynamic, effective teams...
- Sr. Principal Verification Engineer
- Broadcom (Irvine, CA)
- ...of different verification solutions (ie block sims vs. chip sims., Verilog vs. HVL like Specman or Vera , etc.), working knowledge with various verification tools (ie Specman, NC-sim, System Verilog, Debussy, etc.), writing scripts to automate verification process (ie using...
- Sr. Principal Verification Engineer
- Broadcom Corporation (Irvine, CA)
- ...of different verification solutions (ie block sims vs. chip sims., Verilog vs. HVL like Specman or Vera , etc.), working knowledge with various verification tools (ie Specman, NC-sim, System Verilog, Debussy, etc.), writing scripts to automate verification process (ie using...
- ASIC Logic Design and Verification Engineer (Raleigh, NC)
- Qualcomm (Cary, NC)
- ...Design-for-Test, logical equivalency checking, simulation and debug. Engineer should also have significant experience with coding verification testbenches in HVL [ Vera (preferred), SystemVerilog TestBench or e]. Additional Skills Excellent communication skills, both oral and written....
- Engineer Design
- Broadcom (Irvine, CA)
- ...and DFT guidelines. - Able to write test benches in Verilog and/or higher level languages like System Verilog or System C or Vera . - Able to write verification test plans and test cases. - Able to run synthesis, static timing analysis, formal verification . - Understanding of timing...
- Technical Leader , Advanced Verification Technologies
- Cadence Design (San Diego, CA)
- ...of Cadence Advanced Verification products. Position Requirements Position Requirements Extensive experience in creating Coverage Driven Verification environments utilizing e-language tools [SpecMan], Vera , SystemVerilog or SystemC/C++ is required. Track record of successfully...
- Sr. Staff IC Verification Engineer
- Broadcom (San Diego, CA)
- ...technical individual contributor, you will participate in the design verification efforts of Broadcoms highly successful Wireless Personal Area...HW/SW co-simulation. -Experince with Verilog, Verilog PLI, SystemVerilog or Vera , UNIX Scripts, C, Perl, Tcl. -Experience with the...
- Sr. Verification Engineer
- Sun Microsystems (Austin, TX)
- ...work at Sun! ESSENTIAL FUNCTIONS:If you are a senior verification engineer with experience taking a microprocessor core through from...simulation using Verilog- Good understanding of object-oriented programming; The VERA language is a plus- Knowledge of advanced validation techniques...