Vera Verification Engineer Jobs - Browse Keywords

Locations: California, Minnesota, Massachusetts, Texas, North Carolina

Related Keywords: Engineer, Vera, Vera Verification, Verification, Verification Engineer

Sponsored

Sr. Staff IC Verification Engineer: Broadcom (San Diego, CA); ...technical individual contributor, you will participate in the design verification efforts of Broadcoms highly successful Wireless Personal Area...HW/SW co-simulation. -Experince with Verilog, Verilog PLI, SystemVerilog or Vera , UNIX Scripts, C, Perl, Tcl. -Experience with the...; Email this job
TheLadders (10/12/09)
Verification Engineer: Unknown (CA); JOB DESCRIPTION:Successful fabless semiconductor company seekstalented Verification Engineer .As part of the team, you will participate in the verification of highly complex ASICs.QUALIFICATIONS:Knowledge of Verilog, VERA , and networking is preferred.BS in Electrical Engineering...; Email this job
Jobirn.com (11/23/09)

Verification Engineer: Fusion408 (Santa Clara, CA); Verification Engineer Job code: 1255 Job Category: Engineering City: Santa Clara Job Description: Verification ...DSP & PHY layer communication protocols of 802.3 - Experience with Verilog, Vera verification environment, common RTL simulation & verification tools...; Email this job
Fusion408 (11/17/09)
EDA Verification Engineer , Senior: Qualcomm (San Diego, CA); Requisition # G1837043 Job Title EDA Verification Engineer , Senior Post Date 10/27/2009 Division Qualcomm CDMA...four years experience in CAD verification and/or ASIC verification . . Strong knowledge of HVLs( VERA ), HDLs(Verilog/VHDL/SystemVerilog), C/C++/SystemC. RTL...; Email this job
Qualcomm (11/11/09)
Sr. Verification Engineer: Sun Microsystems (Austin, TX); Job Title: Sr. Verification Engineer Requisition Number: 504 Alternate Work Location: None Region: United States...and logic simulation using Verilog - Good understanding of object-oriented programming; The VERA language is a plus - Knowledge of advanced validation techniques such...; Email this job
Sun Microsystems (10/21/09)
Sr. Verification Engineer: Sun Microsystems (Santa Clara, CA); ...your work at Sun!ESSENTIAL FUNCTIONS: If you are a senior verification engineer with experience taking a microprocessor core...simulation using Verilog - Good understanding of object-oriented programming; The VERA language is a plus - Knowledge of advanced validation...; Email this job
Jobirn.com (10/27/09)
ASIC Design And Verification Engineer: Unknown (San Jose, CA); ...languages: C/C++, PERL, PLI is desirable- Familiarity with DSP & PHY layer communication protocols of 802.3- Experience with Verilog, Vera verification environment, common RTL simulation & verification tools- System level & block level verification - Understanding of...; Email this job View duplicates
Jobirn.com (11/01/09)
ASIC Design And Verification Engineer: Terran Systems (San Jose, CA); ...languages: C/C++, PERL, PLI is desirable- Familiarity with DSP & PHY layer communication protocols of 802.3- Experience with Verilog, Vera verification environment, common RTL simulation & verification tools- System level & block level verification - Understanding of...; Email this job
Climber.com (10/23/09)
Sr. Principal Verification Engineer: Broadcom (Irvine, CA); ...Controller Verification team is in need of a Principal design verification engineer who enjoys working in a dynamic and fast-pace...(ie block sims vs. chip sims., Verilog vs. HVL like Specman or Vera , etc.), working knowledge with various verification tools (ie Specman,...; Email this job
Broadcom (11/19/09)
Sr. Principal Verification Engineer: Broadcom Corporation (Irvine, CA); ...Controller Verification team is in need of a Principal design verification engineer who enjoys working in a dynamic and fast-pace...(ie block sims vs. chip sims., Verilog vs. HVL like Specman or Vera , etc.), working knowledge with various verification tools (ie Specman,...; Email this job
Jobirn.com (10/22/09)
Hardware Design Verification Engineer - All Levels: Qualcomm (San Diego, CA); Requisition # G1786475 Job Title Hardware Design Verification Engineer - All Levels Post Date 10/27/2009...solving, debug, adversarial testing * Strong working knowledge of HVLs: VERA /e-Specman * Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting Additional Skills Education...; Email this job
Qualcomm (11/11/09)
Hardware Design Verification Engineer - Modem Communications: Qualcomm (San Diego, CA); Requisition # G1841348 Job Title Hardware Design Verification Engineer - Modem Communications Post Date 10/27/2009...adversarial testing * Strong working knowledge of HVLs: SystemVerilog TB, VERA , or e-Specman * Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting Additional...; Email this job
Qualcomm (11/11/09)

Keyword : Vehicle Simulation - Visual Merchandising Manager International : Venture Partners - Verification Engineer Intel : Vera Verification Engineer Jobs (1 - 10)