- Locations: California, Arizona, Texas, New York, Virginia
- Related Keywords: Calibre, Verification
- Member of Technical Staff, ASIC Design
- GDA Technologies Inc (San Jose, CA)
- ...post-Bachelor's, progressive experience in job offered or as ASIC Design Engineer, in lieu of Master's. Requires Verilog language; - ASIC design & synthesis; - Place & route tools; - Llayout edit tool (like Virtuoso); - Physical verification tools (like Dracula & Calibre ).
- Physical Verification Engineer
- Cxdesign (Correct By Design) (Irvine, CA)
- ...The engineer needs to have a deep understanding on the verifying mix signal block and chip level physical verification with LVS, DRC, ERC, ANT Calibre /Hercules tools and DFM tool. Responsible for maintaining and updating LVS, DRC, ERC, ANT technology files for submicron technology....
- Circuit Design Engineer
- Mindlance (San Diego, CA)
- ...Tool experience using Cadence design suite of tools 5.1.4* and/or 6.1*, Calibre VXL and/or GXL required, Calibre verification suite (DRC,ERC, LVS, Softcheck), Design Management tools preferably using DesignSync. Knowledgeable in layout parasitic effects to deliver quality...
- Engineer, Senior Physical Design
- Marvell (Santa Clara, CA)
- ...Job Sub Category: Digital Design Qualifications: Experienced in chip top integration. Good communication skills and experiences with back-end layout verification tool ( Calibre ) and Layout editor. Prefer in experience with Place and Route tool(ICC, Astro). The candidate will have a BS...
- Engineer, Senior Physical Design
- Marvell Semiconductor, Inc. (Santa Clara, CA)
- ...and reliability of result. Experienced in chip top integration. Good communication skills and experiences with back-end layout verification tool ( Calibre ) and Layout editor. Prefer in experience with Place and Route tool(ICC, Astro).Qualifications:Experienced in chip top integration....
- Engineer, Senior Physical Design
- Marvell Semiconductor, Inc. (Santa Clara, CA)
- ...efficiency and reliability of result. Experienced in chip top integration. Good communication skills and experiences with back-end layout verification tool ( Calibre ) and Layout editor. Prefer in experience with Place and Route tool(ICC, Astro). Qualifications: Experienced in chip top...
- Sr. Physical Design Engineer
- Conexant (Newport Beach, CA)
- ...experience involving flooplanning, design partitioning, clock planning and issues related to routing congestion. - Direct experience with Mentor Calibre verification toolset. Hands-on experience with Physical verification issues including LVS and DRC. - Experience in Power...
- Engineer, Staff Physical Design
- Marvell (Santa Clara, CA)
- ...? Solid knowledge on static timing analysis (PrimeTime), EM/IR-Drop/crosstalk analysis (Celtic, PTSI, Apache, AstroRail), formal or physical verification (Formality, Verplex, Calibre , Hercules) a plus. Description: As a key member of central physical design team, you will provide...
- Mask Layout Designer - Analog/RF IC **Multiple Openings** (Contract)
- Qualcomm (Santa Clara, CA)
- ...errors on completed layouts. Skills/Experience 5+ years RF/Analog and/or Mixed Signal Layout Experience -Cadence Virtuoso XL, DIVA, ASSURA,UNIX, Mentor Calibre verification , Windows based applications -Basic understanding of semiconductor devices as well as CMOS and bipolar processes....
- Physical Verification IC Engineer
- Broadcom (Irvine, CA)
- ...The engineer needs to have a deep understanding on the verifying mix signal block and chip level physical verification with LVS, DRC, ERC, ANT Calibre /Hercules tools and DFM tool. Responsible for maintaining and updating LVS, DRC, ERC, ANT technology files for submicron technology....
- Physical Verification Engineer
- Cxdesign (Correct By Design) (Irvine, CA)
- ...The engineer needs to have a deep understanding on the verifying mix signal block and chip level physical verification with LVS, DRC, ERC, ANT Calibre /Hercules tools and DFM tool. Responsible for maintaining and updating LVS, DRC, ERC, ANT technology files for submicron technology....
- IHS-09:0010: Senior Energy Analyst
- CALIBRE Systems, Inc. (Crystal City, VA)
- ...The following certifications are desired: Registered Professional Engineer, Certified Energy Manager (CEM), Certified Measurement and Verification Professional (CMVP). Minimum Level of Education: (Other education, commensurate experience and demonstrated ability of individual...
- Engineer, Senior Physical Design
- Marvell Semiconductor, Inc. (Santa Clara, CA)
- ...and reliability of result. Experienced in chip top integration. Good communication skills and experiences with back-end layout verification tool ( Calibre ) and Layout editor. Prefer in experience with Place and Route tool(ICC, Astro).Qualifications:Experienced in chip top integration....
- Physical Verification IC Engineer
- Broadcom Corporation (Irvine, CA)
- ...The engineer needs to have a deep understanding on the verifying mix signal block and chip level physical verification with LVS, DRC, ERC, ANT Calibre /Hercules tools and DFM tool. Responsible for maintaining and updating LVS, DRC, ERC, ANT technology files for submicron technology....