- Locations: California, Texas, Iowa, Massachusetts, Ohio
- Related Keywords: DRC, DRC LVS, LVS, Layout, Layout DRC LVS, Verification, Verification DRC LVS
- Physical Design Verification Engineer
- Sun Microsystems (Santa Clara, CA)
- ...Sun Microsystems is looking for a highly motivated Physical Design Verification Engineer. Responsibilities for this position include Development, Testing and...responsibilities for this position include :* Implementing DRC , lvs , erc, antenna, and other layout post processing...
- Physical Design Verification Engineer
- Sun Microsystems (Santa Clara, CA)
- ...Sun Microsystems is looking for a highly motivated Physical Design Verification Engineer. Responsibilities for this position include Development, Testing and Support...for this position include : * Implementing DRC , lvs , erc, antenna, and other layout post processing rules...
- CAD Manager - RF - RFIC - Mixed-Signal - Analog - DRC - LVS
- CyberCoders Engineering (San Jose, CA)
- ...as of 11/23/2009. CAD Manager - RF - RFIC - Mixed-Signal - Analog - DRC - LVS - pCell - SKILL - PERL - Python -...Analog DRC , LVS , and PRE runset development, as well as verification for top-level mixed signal designs - Excellent knowledge of SKILL, PERL/Python, and TCL...
- CAD Manager - RF - RFIC - Mixed-Signal - Analog - DRC - LVS
- Cybercoders.com (CA)
- CAD Manager - RF - RFIC - Mixed-Signal - Analog - DRC - LVS CAD Manager - RF - RFIC - Mixed-Signal - Analog - ...Analog DRC , LVS , and PRE runset development, as well as verification for top-level mixed signal designs - Excellent knowledge of SKILL, PERL/Python, and TCL...
- Physical Verification & Extraction Engineer
- Qualcomm (San Diego, CA)
- ...Qualcomm CDMA Technology Job Area Engineering - Hardware Location California - San Diego Job Description Develop and support solutions for layout verification ( DRC / LVS ) and parasitic extraction of VLSI designs for timing, power-grid and signal integrity analysis. In this...
- Experienced IC Layout and DRC Software Developers
- Silvaco (Santa Clara, CA)
- ...or Ph.D in CS/CE/Mathematics * Minimum 3 years of DRC development experience * Strong in C/C++ * Experience in IC physical verification software. * Experience in EDA software design, IC Layout , DRC , ERC, LVS and LPE. Apply Please quote ref. SW-CAD-CA when applying By Email
- Senior CAD Engineer
- SanDisk (Milpitas, CA)
- ...In this position, the individual will be responsible for developing/supporting physical verification rule decks ( LVS / DRC /ERC) for the layout group, completing placement and routing flow/methodology development, developing/supporting/calibrating parasitic extraction flow...
- Analoc IC/ RF/ RFIC Design Engineers
- Unknown (Santa Clara, CA)
- ...for performance and size- Design implementation skills (eg, custom layout , synthesis-> auto place and route flow)- Proficiency in layout verification , DRC , LVS - Knowledge of scripting/language (perl, shell, tcl, skill) - Advanced laboratory measurement skills (analog,...
- CAD Engineer I
- SanDisk (Milpitas, CA)
- ...In this position, the individual will be responsible for developing and supporting physical verification rule decks ( LVS / DRC /ERC) for layout group. The individual will also complete placement and routing flow/methodology development, develop/support/calibrate parasitic...
- Analog Design Engineer
- Unknown (Austin, TX)
- ...performance and size* Design implementation skills (eg, custom layout , synthesis -andgt; autoplace and route flow)* Proficiency in layout verification , DRC , LVS * Knowledge of scripting/language (perl, shell, tcl, skill)* Advanced laboratory measurement skills (analog,...
- Senior CAD Engineer
- SanDisk (Milpitas, CA)
- ...do. In this position, the individual will be responsible for developing/supporting physical verification rule decks ( LVS / DRC /ERC) for the layout group, completing placement and routing flow/methodology development, developing/supporting/calibrating parasitic extraction flow for...
- IC Layout /Mask Designer
- FLIR Systems (Santa Barbara, CA)
- IC Layout /Mask Designer Santa Barbara, CA United States Job ID: 1961 Job Type: Full Time Location:...electrical schematic drawings to manufacturable IC designs by creating GDS databases ? DRC and LVS ROIC Design Verification ? Ensure designs conform to wafer manufacturer?s...
- Senior IC Layout Designer
- Maxim (Austin, TX)
- ...successful candidate must be a self starter and motivated to excel. Knowledge of Linux and Cadence required. Calibre verification experience a plus. Requires a thorough understanding of DRC and LVS layout verifications. Experience taking a chip from planning stage through tape...
- Analog Design Engineer
- Unknown (Austin, TX)
- ...performance and size* Design implementation skills (eg, custom layout , synthesis -andgt; autoplace and route flow)* Proficiency in layout verification , DRC , LVS * Knowledge of scripting/language (perl, shell, tcl, skill)* Advanced laboratory measurement skills (analog,...