- Locations: California, Arizona, Oregon, Massachusetts, New Jersey
- Related Keywords: Systemc, Verification
- Wpan IC Design Engineer
- Broadcom (San Diego, CA)
- ...team member, you will contribute to the design, development and verification of Broadcoms highly successful Wireless SOCs. Responsibilities include: Lead...to the ASIC development process including Verilog, VHDL and C /C++/ SystemC . Strong analytical, and problem solving skills as well...
- Chip Verification Lead
- GDA Technologies Inc (San Jose, CA)
- Perform chip verification (including development of methodologies, test plans, compliance test suite, test bench creation, & test cases) using System Verilog, SystemC , C++, & VERA; Develop scripts; Develop test bench components (like BFM, transactors, assertions, coverage,...
- ASIC Design Engineer
- 3Leaf Systems (Santa Clara, CA)
- ...and desire to work in a team environment. Additional skills: - Working experience of 10G Ethernet and/or InfiniBand. - Experience with SystemC verification environments. - Experience working in a lab debug environment - Xilinx FPGA design, debug, and test - Knowledge of Perl and...
- VLSI Design Automation Engineer (functional verification and ESL), Senior/Staff
- Qualcomm (San Diego, CA)
- ...design, design (hw/sw) verification tools and techniques, computer architecture, etc. - Familiar with design and verification languages: VHDL, Verilog, System Verilog, SystemC , C/C++, assembly, Vera, SVTB, SVA, etc. - Experience in front-end EDA tools: HDL simulators (eg Questa,...
- Technical Leader , Advanced Verification Technologies
- Cadence Design (San Diego, CA)
- Technical Leader for Advanced Verification Methodologies Position Description As a Technical Leader in Cadence?s ...Verification environments utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC /C++ is required. Track record of successfully verifying complex ASICs is...
- Senior Engineer, ASIC Verification
- Marvell (Santa Clara, CA)
- Job Title: Senior Engineer, ASIC Verification Job Category: Engineering Job Sub Category: Design Verification Qualifications:...and Perl. Experience with Verilog coding and Verilog PLI. Knowledge of SystemC , SytemVerilog and assertion-based language and methodology is a plus. Good...
- Associate Technical Marketing Engineer
- Mentor Graphics (Wilsonville, OR)
- ...preferred), recent college graduate, and demonstrated experience in the following areas: High Level Verification (VHDL, Verilog, System Verilog, SystemC , constrained random, assertions). Strong group or customer presentation skills are required, excellent interpersonal...
- Director/Principal Engineer of Design Verification and Validation - Wireless Communications
- Qualcomm (San Diego, CA)
- ...finish?strong track record on execution. Wireless system design or architecture experience and knowledge required. Experience with directed random verification in SystemVerilog, Vera, Verisity/Specman and/or SystemC preferred. You should have experience leading dynamic, effective teams...
- Sr. Verification System Engineers
- Comrise (Bridgewater, NJ)
- Sr. Verification System Engineers Job ID: 18380 # Positions: 5 Location: US-NJ-Bridgewater Experience (Years): 5... using models generated from multiple tools such as Matlab/Simulink, SPW, C++, SystemC , CoWare, etc 4. Experience with wireless communications, FPGA, firmware, etc 5....
- Technical Leader , Advanced Verification Technologies
- Cadence Design (San Diego, CA)
- Technical Leader for Advanced Verification Methodologies Position Description As a Technical Leader in Cadence?s ...Verification environments utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC /C++ is required. Track record of successfully verifying complex ASICs is...
- EDA Verification Engineer, Senior
- Qualcomm (San Diego, CA)
- ...communicate, coordinate and educate Skills/Experience . Prefer two to four years experience in CAD verification and/or ASIC verification . . Strong knowledge of HVLs(VERA), HDLs(Verilog/VHDL/SystemVerilog), C/C++/ SystemC . RTL simulation (ModelSim, VCS, Vera), Formal verification ...
- ASIC Verification Engineer - Acceleration
- Broadcom (Santa Clara, CA)
- ...join a focused and professional team engaged in design verification using hardware acceleration on highly integrated SOCs. The successful...with Perl, Linux/UNIX Expertise with Verilog Expertise with C/C++ ( SystemC a plus) Expertise with major industry RTL simulator Experience...
- Principal Hardware Verification Engineer
- Starent Networks Corporation (Tewksbury, MA)
- ...skills - verbal and written are required. Strong experience in FPGA RTL design in Verilog Skills:* SystemVerilog and/or systemC or similar high-level verification language.* Verilog and/or VHDL experience required.* Minimum 5 years verification experience.* Ability to code in a...
- Design Verification Engineer
- STEC, Inc. (San Diego, CA)
- ...architects and flash characterization teams to plan and execute verification and validation of ASIC and IP blocks and supporting...Master's Electrical Engineering and at least 3 to 5 years of applicable experience Skills/Experience- Verilog/VHDL coding, SystemC , SystemVerilog, OVM