- Locations: California, Colorado, Maryland, Massachusetts, Minnesota
- Related Keywords: Systemverilog, Verification
- Verification engineer( SystemVerilog /VMM)
- Synapse Design Automation Inc (Chandler, AZ)
- Job Specification: In this role you will be responsible for functional verification MUST HAVE experience with SystemVerilog and VMM Create constrained random tests Utilize DPI to interface to external languagesRun backannotated gate level timing simulations Write tools and scripts in...
- Principal Hardware Verification Engineer
- Starent Networks Corporation (Tewksbury, MA)
- ...skills - verbal and written are required. Strong experience in FPGA RTL design in Verilog Skills:* SystemVerilog and/or systemC or similar high-level verification language.* Verilog and/or VHDL experience required.* Minimum 5 years verification experience.* Ability to code...
- Verification engineer( SystemVerilog /VMM)
- Synapse Design Automation Inc (Chandler, AZ)
- Job Specification: In this role you will be responsible for functional verification MUST HAVE experience with SystemVerilog and VMM Create constrained random tests Utilize DPI to interface to external languagesRun backannotated gate level timing simulations Write tools and scripts in...
- Verification engineer( SystemVerilog /VMM)
- Synapse Design Automation Inc (Chandler, AZ)
- Job Specification : In this role you will be responsible for functional verification MUST HAVE experience with SystemVerilog and VMM Create constrained random tests Utilize DPI to interface to external languages Run backannotated gate level timing simulations Write tools and scripts in...
- Director/Principal Engineer of Design Verification and Validation - Wireless Communications
- Qualcomm (San Diego, CA)
- ...finish?strong track record on execution. Wireless system design or architecture experience and knowledge required. Experience with directed random verification in SystemVerilog , Vera, Verisity/Specman and/or SystemC preferred. You should have experience leading dynamic, effective teams...
- Sr. Verification Engineer
- Baytech Solutions (Westlake Village, CA)
- ...verification plan and executing the test plan using SystemVerilog for next generation Mixed-Signal products. He/she will also contribute.../test plan for next generation Mixed-Signal products. - Execute verification plan using SystemVerilog /Verilog using both direct and...
- ASIC Verification Intern
- Innovative Logic Inc. (Santa Clara, CA)
- ...blocks of our next generation USB3.0 IP. All the work will be done in systemverilog . You must have good understanding of systemverilog along with verification flow and use of verification tools such as Modelsim. It is an excellent opportunity for you to use this as relevant...
- ASIC Verification Intern
- Innovative Logic Inc. (Santa Clara, CA)
- ...blocks of our next generation USB3.0 IP. All the work will be done in systemverilog . You must have good understanding of systemverilog along with verification flow and use of verification tools such as Modelsim. It is an excellent opportunity for you to use this as relevant...
- Engineer, Senior Design
- Marvell (Santa Clara, CA)
- ...design experience. Must have at least 3 years of logic deisgn. Must possess at least 3 years work experience with SystemVerilog for verification . Must have at least 3 years experience in Constrained Randomized verification environment development. Description: RTL coding and...
- Engineer, Senior Design
- Marvell (Santa Clara, CA)
- ...Knowledge in C++ is a must. Experience with place-and-route and gate-level circuit design a plus. Experience with SystemVerilog for verification a plus. Research or industrial experience in Error Correction algorithm implementation is desirable Description: Architecture definition, RTL...
- Principal FPGA Designer (m)
- SAIC (Columbia, MD)
- ... performing design trade-offs to achieve operational frequency (~200 MHz) with minimal resource utilization. Responsible for verification of modules using SystemVerilog , creating and maintaining design and verification documentation throughout the development process, and adhering...
- Principal FPGA Designer (m)
- SAIC (Columbia, MD)
- ... performing design trade-offs to achieve operational frequency (~200 MHz) with minimal resource utilization. Responsible for verification of modules using SystemVerilog , creating and maintaining design and verification documentation throughout the development process, and adhering...
- ASIC Verification Intern
- Innovative Logic Inc. (Santa Clara, CA)
- ...blocks of our next generation USB3.0 IP. All the work will be done in systemverilog . You must have good understanding of systemverilog along with verification flow and use of verification tools such as Modelsim. It is an excellent opportunity for you to use this as relevant...
- Engineer
- Mentor Graphics (Longmont, CO)
- ENGINEERApplications, Longmont, CO: contact potential customers to drive sales of Mentor Graphics' IC functional verification design tools; assist customers in conducting product evals & using these tools; develop/deliver product demos/tech presentations.Reqs:MS in EE or CompEng &...