Verilog ASIC Engineer Jobs - Browse Keywords

Locations: California, Utah, Colorado, Texas, South Dakota

Related Keywords: ASIC, ASIC Engineer, ASIC Verilog, Engineer, Verilog, Verilog Engineer

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ASIC Verification Engineer: Brocade Communications Systems, Inc. (San Jose, CA); This individual will be a key member of the ASIC system level verification team. Responsibilities will include developing the verification...also needs to have a full understanding of design using Verilog , and working experience with C/C++.At least 5+ years in...; Email this job
JobFox.com (09/09/09)
Member of Technical Staff, ASIC Design: GDA Technologies Inc (San Jose, CA); ...Eng or Electrical Eng with 5 yrs of related, post-Bachelor's, progressive experience in job offered or as ASIC Design Engineer , in lieu of Master's. Requires Verilog language; - ASIC design & synthesis; - Place & route tools; - Llayout edit tool (like Virtuoso); -...; Email this job
JobFox.com (09/14/09)

Engineer - ASIC Design: SafeNet Inc. (Torrance, CA); Engineer - ASIC Design Job ID: 1313 # Positions: 1 Location: US-CA-Torrance Experience (Years): 3... ASIC design; detailed design requirements, architecture design, VHDL or Verilog RTL detailed design, simulation, synthesis, timing analysis, test vector generation; creating...; Email this job
SafeNet (10/14/09)
Sr. ASIC Design Engineer: Enphase Energy (Petaluma, CA); ...and Filters * Knowledge of low-level communications protocols (L1/L2) strongly desired. * Knowledge of all phases of ASIC design methodology including Verilog Coding, Synthesis, DFT, ATPG, Chip Constraints, Timing Closure, Verification. * Silicon lab bring up experience *...; Email this job
Penn Energy.com (10/23/09)
ASIC Design Engineer: Cybercoders.com (CA); ASIC Design Engineer ASIC Design Engineer Skills Required Asic Design, Verilog , RTL, Design for Test, Logic, Digital Design, SoC If you are a ASIC Design Engineer with at least 6 years experience and live in or within commuting distance to San Jose, CA, please...; Email this job
ExpatJob.net (10/22/09)
ASIC Design and Verification Engineer: QLogic (Shakopee, MN); ASIC Design and Verification Engineer Tracking Code 3390 Job Description QLogic simplifies the process of networking...Minnesota facility. Job responsibilities include: * Design blocks of logic using Verilog or VHDL hardware languages * Analyze functional specifications and test...; Email this job
QLogic (09/29/09)
ASIC Design Engineer: Brocade (San Jose, CA); Job Title: ASIC Design Engineer Requisition #: 2117 Function: Engineering Country: United States State: California City:...simulation / synthesis / formal verification tools. . Complete familiarity with Verilog from simulation and synthesis point of view. . Full understanding...; Email this job
Brocade (09/02/09)
ASIC Design Engineer: Brocade (San Jose, CA); Job Title: ASIC Design Engineer Requisition #: 2024 Function: Engineering Country: United States State: California City:...simulation / synthesis / formal verification tools. . Complete familiarity with Verilog from simulation and synthesis point of view. . Full understanding...; Email this job
Brocade (09/08/09)
ASIC Physical Design Engineer: Brocade (San Jose, CA); Job Title: ASIC Physical Design Engineer Requisition #: 2119 Function: Engineering Country:...with Verilog , synthesis flow, DC/DCT/DCG, formal verification and Conformal ASIC or Formality . Strong hands-on experience of floorplan/placement/CTS/routing in hierarchical...; Email this job
Brocade (09/02/09)
ASIC Design Engineer: Brocade (San Jose, CA); ...Jose Travel Requirements: None Position Type: Employee Job Description: ASIC Engineer (Design or Verification) Seeking self-motivated,.../ synthesis / formal verification tools. Complete familiarity with Verilog from simulation and synthesis point of view. Full...; Email this job
Brocade (09/02/09)
Design Automation Engineer - Hardware Tools for Front-End ASIC Design (C++, Perl) - R&D: Qualcomm (San Diego, CA); Requisition # E1851381 Job Title Design Automation Engineer - Hardware Tools for Front-End ASIC Design (C++, Perl) -...design, timing and electrical analysis, and a good working knowledge of verilog or VHDL, and practical experience in chip development and tape-out are...; Email this job
Qualcomm (11/17/09)
Engineer , Senior ASIC Design: Marvell (Santa Clara, CA); Job Title: Engineer , Senior ASIC Design Job Category: Engineering Job Sub Category: Design Verification Qualifications: Masters...and assertion-based language and methodology is a plus. Good C/C++ and Verilog debugging skills. Description: Marvell is seeking engineer with...; Email this job View duplicates
Marvell (09/15/09)

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