- Locations: California, Texas, Ohio, Colorado, Massachusetts
- Related Keywords: Based, Verilog, Verilog Based Internship
- Design Verification Engineers
- New NYC Opportunity! (New York, NY)
- ...involves working closely with design engineers to create constrained random based test-bench and test cases, to ensure adequate feature and...verification test languages such as Vera. Knowledge of VHDL or Verilog language and using synthesis tools is desired. ~Implement the...
- SRAM Design Engineer
- Sun Microsystems (Austin, TX)
- ...is to design and develop high speed embedded SRAMs for server- based processors. These SRAMs are planned, developed, and verified at...optimum design plan. Transistor level understanding of operation, layout experience, SPICE/ Verilog usage and tool expertise, as well as experience in...
- ASIC Verification Engineer - Digital
- Zoran Corporation (Sunnyvale, CA)
- ...and chip level functionality in a complex SOC environment. Successful applicant will have verification experience and a solid understanding of Verilog based RTL design. This work involves working closely with design engineers to create constrained random based test-bench and test...
- FPGA Design Engineer Consultant Contractor
- Intevac (Santa Clara, CA)
- ...Camera Link, Gigabit Ethernet, NTSC, PCI, LCDs, etc. Tools: Altera Quartus Tool flow such as TimeQuest, SignalTap, PowerPlay Power Analyzer. Verilog /System Verilog Assertions based verification. Ability to work sometimes i Required Experience Tools : Knowledge of Verilog is...
- FPGA Logic Design Engineer
- Intevac (Santa Clara, CA)
- ...Camera Link, Gigabit Ethernet, NTSC, PCI, LCDs, etc.Tools: Altera Quartus Tool flow such as TimeQuest, SignalTap, PowerPlay Power Analyzer. Verilog /System Verilog Assertions based verification.Ability to work sometimes individually or as part of a small team.To be motivated and...
- ASIC Verification Engineer - Digital Video
- Zoran Corporation (Sunnyvale, CA)
- ...level functionality in a complex SOC environment. Successful application will have significant verification experience and a solid understanding of Verilog based RTL design. This work involves working closely with design engineers to create constrained random based test-bench and...
- Sr FPGA Verification Engineer
- Intuitive Surgical, Inc. (Sunnyvale, CA)
- ...design and verification * Perform Logic verification at module and system level. Experience in constrained pseudo-random verification, System Verilog and assertion based verification are desired * Ability to conduct static timing verification; familiarity with Xilinx tools is a plus *...
- Verification Engineer
- Denali Software (Austin, TX)
- ...with design IP coded in Verilog Test builder experience Exposure to synthesis and STA reports and analysis Debug expertise in tool flow for Verilog based designs and netlists Understanding of simulation, synthesis and static timing products and their interfaces. BSEE or equivalent
- FPGA Design Engineer Consultant Contractor
- Intevac (Santa Clara, CA)
- ...Camera Link, Gigabit Ethernet, NTSC, PCI, LCDs, etc. ?Tools: Altera Quartus Tool flow such as TimeQuest, SignalTap, PowerPlay Power Analyzer. Verilog /System Verilog Assertions based verification. ?Ability to work sometimes individually or as part of a small team ?To be motivated...
- FPGA Logic Design Engineer
- Intevac (Santa Clara, CA)
- ...Camera Link, Gigabit Ethernet, NTSC, PCI, LCDs, etc.Tools: Altera Quartus Tool flow such as TimeQuest, SignalTap, PowerPlay Power Analyzer. Verilog /System Verilog Assertions based verification.Ability to work sometimes individually or as part of a small team.To be motivated and...
- Senior/Principal ASIC Design Engineer
- talentfuse (Phoenix, AR)
- ...Interface & Register Map, and CODEC integration. Requirements: . 10+ years in Digital Design, at least 5+ years in Verilog /Synthesis based ASIC Design. . Verilog language & simulation verification experience. . Mixed-signal simulation (Cadence AMS), interfacing with analog...
- ASIC Design Engineer
- MIT Lincoln Laboratory (Lexington, MA)
- ...testing. Minimum of 3 years experience in above areas. The following experience is desired: FPGA and standard cell ASIC design VHDL and Verilog based compilation designs RTL level design High speed designs 3rd party IPs usage such as FIFO, SRAM, and register file generators Testability...
- Verification Engineer
- Denali Software (Austin, TX)
- ...with design IP coded in Verilog Test builder experience Exposure to synthesis and STA reports and analysis Debug expertise in tool flow for Verilog based designs and netlists Understanding of simulation, synthesis and static timing products and their interfaces. BSEE or equivalent
- Digital Hardware Engineer
- Johns Hopkins University Applied Physics Laboratory (Laurel, MD)
- ...for the DOD and Intelligence Community. Design and prototype FPGA- based digital devices and DSP chip- based processors suitable...processing concepts. Co-op work experience, familiarity with VHDL or VeriLog and FPGA development tools. Willingness to work on quick-reaction...