- Locations: California, Ohio, Texas, Colorado, Illinois
- Related Keywords: Design, Physical, Physical Design, Verilog
- Analog Design Engineer
- Enphase Energy (Petaluma, CA)
- ...the way to lab debug/characterization's. * Experienced in analog circuit design , circuit simulation, verification and physical layout. *... environment, analog circuit simulation tools (HSpice or Spectre), and Verilog . * Work closely with IC layout/mask designers, provide floorplan...
- Design Verification Engineer
- NXP Semiconductors (San Jose, CA)
- ...You will interface with logic designers, architects, software engineers, and physical design engineers to develop and execute test...working knowledge of assertions and formal verification - Experience in Verilog , C/C++ and scripting languages - Working knowledge of CMOS...
- ASIC Physical Design Engineer
- Brocade (San Jose, CA)
- Job Title: ASIC Physical Design Engineer Requisition #: 2119 Function: Engineering Country: United States State: California City:...and Experience . Knowledgeable of libraries - .lib and .lef, logic design and DFT . Familiar with Verilog , synthesis flow, DC/DCT/DCG,...
- Engineer, Staff Physical Design
- Marvell (Santa Clara, CA)
- Job Title: Engineer, Staff Physical Design Job Category: Engineering Job Sub Category: Digital Design ...design strategies, methodologies and deep sub-micron technology issues. Familiar with ASIC design flow, Verilog HDL, synthesis and timing closure. ? Successfully...
- Senior Physical Design Engineer
- Sun Microsystems (Austin, TX)
- Job Title: Senior Physical Design Engineer Requisition Number: 548 Alternate Work Location: None Region: United...modeling, logic design , and synthesis, and excellent coding skills in Verilog or another high-level language. Education and Experience: YEARS OF EXPERIENCE: 15+...
- Staff Physical /ASIC Design Engineer
- Zoran Corporation (Sunnyvale, CA)
- ... Engineer Sunnyvale, CA - Hardware/VLSI Engineering Primary function: Perform physical design , timing closure, and tape out functions for...Programming skills in perl, tcl, and C are strongly favored. Knowledge in Verilog RTL and gate-level netlist structures are also preferred.
- ASIC Design And Verification Engineer
- Terran Systems (San Jose, CA)
- ASIC Verification Requirements: Position OverviewProspective candidate will design verification of a high performance physical layer...hands on development of test bench- Test case development using VERA/ VERILOG - Design /Develop models for test environment setup- Run...
- ASIC Design And Verification Engineer
- Unknown (San Jose, CA)
- ... AND VERIFICATION ENGINEERASIC Verification Requirements:Position OverviewProspective candidate will design verification of a high performance physical ...on development of test bench- Test case development using VERA/ VERILOG - Design /Develop models for test environment setup-...
- Sr. Design Methodology Engineer
- Nvidia (Santa Clara, CA)
- ...or Computer Engineering, MS preferred - 5 years minimum experience with Verilog and Synopsys development environment, tools, script writing - Design...Analysis. - Design Experience in formal equivalence checking. - Physical Design knowledge or experience is helpful. - Prefer...
- Senior Chip Design Engineer
- Apple (Cupertino, CA)
- ...be responsible for taking designs from specification or RTL through physical design using both custom and semi-custom implementation techniques....- BSEE and 10+ years experience in high performance semiconductor design - Experience with Verilog - Understanding of CMOS...
- ASIC Design and Verification Engineer
- QLogic (Shakopee, MN)
- ...Engineer at our Shakopee, Minnesota facility. Job responsibilities include: * Design blocks of logic using Verilog or VHDL hardware...Investigate area and power reductions * Support timing closure of physical design This position requires independent thinking to resolve...
- Sr. Digital Design & Verification Engineer
- Fairchild Imaging (Milpitas, CA)
- ...test plans, verification test benches, and perform debugging tests, STA, Verilog modeling, simulation, physical place & route, timing...coding, verification, gate level simulation, and associated tools. Experience in physical design , place and route, static timing analysis...
- Analog Design Engineer
- ON Semiconductor (Austin, TX)
- As an Analog Design Engineer in the Corporate R&D group, you will:Focus on PLL, DLL, POR, CMOS IO, ADC, DAC,...scripting, Skill, etc. A working knowledge of RTL flow from description out to physical gates using automated tool flows. Timing and power concerns as well as automated...
- Hardware Development Eng
- Panduit (IL)
- ...a lifetime. The primary responsibility will be to develop, design , and implement electronic state of the art circuit boards...and/or Orcad Tool Suites, SPICE simulations, Assembly Programming, C-Programming, Verilog , VHDL, FPGA/CPLD Vendor tools, Microsoft Office and Microsoft Project...