- Meta (Austin, TX)
- …of our industry leading virtual and augmented reality systems.As a Design Verification Engineer (DVEs), you will be a key contributor in planning, reviewing and ... efforts at the IP and sub-system levels. You will collaborate in improving DV methodologies and establishing best practices. Your expertise is needed in all phases… more
- Qualcomm (Austin, TX)
- …Group, Engineering Group > CPU Engineering **General Summary:** As a Design Verification Engineer , you will work with Chip Architects to validate the concepts of CPU ... for your functional domain. + Execute Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and… more
- Meta (Austin, TX)
- …Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Lead the DV effort ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking...Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team… more
- Meta (Austin, TX)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team...Hands-on experience in verifying a IP block using standard DV based techniques. 8. Experience in EDA tools and… more