• Lead Static Timing

    The Boeing Company (El Segundo, CA)
    …with us. Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for a Senior Static Timing Analysis (STA) engineer to join us as part of ... Strike, Surveillance and Mobility; and Autonomous Systems). As a Static Timing Analysis (STA) Engineer...considerations. **Typical Summary Pay Range:** Summary pay range for Lead Level: $126,650 - $171,350 Applications for this position… more
    The Boeing Company (05/20/24)
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  • Synthesis/STA Engineer

    Qualcomm (Santa Clara, CA)
    …Power with low power design team and implement various optimization techniques to reduce power. Lead Static Timing Analysis , work closely with CAD teams ... on PD STA flow integration and updates; Lead Timing Closure with Automated ECO tools,...Strong Expertise with PrimeTime (PT) for PreLayout and PostLayout Static Timing Analysis + Experience… more
    Qualcomm (04/18/24)
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  • CPU Timing Convergence Lead

    Google (Mountain View, CA)
    …or a related field, or equivalent practical experience. + 5 years of experience with Static Timing Analysis . + Experience in high speed design timing ... Knowledge of semiconductor device physics and transistor characteristics. + Understanding of Static Timing Analysis including sign-off corner definitions,… more
    Google (05/03/24)
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  • Sr. Principal STA Solutions Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    analysis , place and route, extraction, spice etc. Job Responsibilities: . Perform Static timing analysis , glitch, noise analysis , extraction using ... RC Extraction, power and UPF/CPF concepts. . Execute and lead Tempus timing signoff campaigns at existing...VLSI, Semiconductor, Electrical or Computer Engineering. + Expert in Static Timing Analysis with knowledge… more
    Cadence Design Systems, Inc. (05/31/24)
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  • Senior/ Lead RTL to GDSII Digital…

    Cadence Design Systems, Inc. (Austin, TX)
    …Equivalence Checking Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required. Good hands-on ... Signoff including Synthesis, Place and Route, Design Closure, and timing /power signoff, RTL to GDSII. Lead technical...experience of Floorplanning , Place and Route, Timing analysis and Sign-off, preferable with CDNS… more
    Cadence Design Systems, Inc. (03/23/24)
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  • 3D IC Solutions Engineer- Signal/Power Integrity…

    Siemens Digital Industries Software (Fremont, CA)
    …validate the extraction scripts to facilitate a package level Static Timing Analysis (STA) workflow. The SI/PI Lead will work with the Package and IC ... performing individual for an opportunity to serve as the Signal/Power Integrity Analysis Lead in our 3D IC Solutions Engineering team in driving the development… more
    Siemens Digital Industries Software (05/26/24)
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  • EDAP Technical Lead

    KBR (Chantilly, VA)
    …tools for collaboration, continuous end-to-end integration and delivery, software development, static code analysis , and test management. + Experience using ... Title: EDAP Technical Lead Belong. Connect. Grow. with KBR! Are you...further. Dive into the world of intelligence gathering and analysis with our top-tier intel unit. You'll work alongside… more
    KBR (04/07/24)
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  • Lead IC Digital Implementation Application…

    Cadence Design Systems, Inc. (San Jose, CA)
    …design/EDA experience Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required Prior experience ... and Signoff including Place and Route, Design Closure, and timing /power signoff Guide customers on how to best utilize...tools including Place and Route, IR Drop, backend design timing and power closure Experience with advanced nodes 10nm… more
    Cadence Design Systems, Inc. (04/10/24)
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  • AvionX Hardware Engineer - FPGA/Firmware…

    The Boeing Company (Hazelwood, MO)
    …Integrate DSP IP from Boeing's algorithm team and third-party IP as needed + Perform static timing analysis , LEC, CDC, linting, and other necessary checks to ... in the full development lifecycle of hardware including requirements analysis , design, build, integration, test, certification, production. Exceptional candidates… more
    The Boeing Company (05/24/24)
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  • Solutions Group Director

    Cadence Design Systems, Inc. (Austin, TX)
    …qualified candidate must have demonstrated leadership with successful tapeouts in the field of static timing analysis , hands-on expertise with tool, flow, & ... engineering and other members of solution team. Responsibilities: * Lead customer engagement for Cadence signoff product ( timing...signoff, eco and iR * Subject domain expert in static timing analysis * Hands-on… more
    Cadence Design Systems, Inc. (05/08/24)
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  • Lead Semiconductor Engineer

    Honeywell (Phoenix, AZ)
    …Key Responsibilities + Build Requirements, Design and Simulation + Conduct Code Synthesis + Static Timing Analysis / Timing Closure + Integration and Test ... Support + Provide Customer Support + Prepare Documentation + Mentor junior engineers + ASIC/FPGA design using Verilog/VHDL and/or verification using System Verilog/UVM + Good VHDL or Verilog working knowledge + Some travel within US/International may be… more
    Honeywell (03/22/24)
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  • ASIC and/or FPGA Design & Verification Engineer…

    The Boeing Company (El Segundo, CA)
    …Integrate DSP IP from Boeing's algorithm team and third-party IP as needed + Perform static timing analysis , LEC, CDC, linting, and other necessary checks to ... multiple ASIC and/or FPGA Design and Verification Engineers at Lead , Senior & Principal levels to join us as...Engineer on the Boeing Electronic Products team you will lead a growing team and develop state-of-the-art digital ICs/SoCs… more
    The Boeing Company (05/26/24)
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  • ASIC and/or FPGA Design & Verification Engineer…

    The Boeing Company (Mountain View, CA)
    …Integrate DSP IP from Boeing's algorithm team and third-party IP as needed + Perform static timing analysis , LEC, CDC, linting, and other necessary checks to ... multiple **ASIC and/or FPGA Design and Verification Engineers** at Lead , Senior & Principal levels to join us as...Engineer on the Boeing Electronic Products team you will lead a growing team and develop state-of-the-art digital ICs/SoCs… more
    The Boeing Company (05/18/24)
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  • Lead Application Engineer - Physical Design

    Cadence Design Systems, Inc. (San Jose, CA)
    …experience is a must. + Must be familiar with digital Place and Route methodology, static timing analysis and at least one scripting language such as ... perl or TCL. + Must have excellent debugging skills and an ability to separate out the critical issues from trivial ones. + Must possess superior communication skills, an outgoing personality and an ability to build a rapport with the customer + Be proud and… more
    Cadence Design Systems, Inc. (04/06/24)
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  • Lead Digital Implementation Applications…

    Cadence Design Systems, Inc. (San Jose, CA)
    …EDA tools is required, ie; Genus, Design Compiler, Innovus, ICC2, Conformal, Tempus, STA, Static Timing Analysis , PrimeTime, Modus, and/or Voltus is highly ... desired + Experience in a scripting language such as TCL/Perl/Python + MS in EE or CE with 6-8 years' experience or BS with 8+ years' experience + Candidate should have strong customer-facing communication and problem solving skills + Strong personal drive for… more
    Cadence Design Systems, Inc. (05/10/24)
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  • PNT Engineer

    KBR (Dayton, OH)
    Title: PNT Engineer National Security Solutions (NSS) Positioning, Navigation and Timing (PNT) Engineer Job Title: PNT Engineer Who We Are KBR Government Solutions ... development skills with desired experience in Position, Navigation and Timing (PNT), Global Navigation Satellite Systems (GNSS), or other...physical setup and measurement of results, as well as analysis and reporting of the findings. This job also… more
    KBR (04/17/24)
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  • Project Engineer - Brake Systems

    Cummins Inc. (Troy, MI)
    …engineers and supplier partners to deliver information and recommendations that lead to quality product decisions. + Applies academic knowledge and existing ... of these decisions include day to day project details, analysis or test work instruction details, coordination across discipline...with greater elements of ambiguity over the senior or lead engineer level and with full accountability to the… more
    Cummins Inc. (03/06/24)
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  • Magna Generic Job Profile - Canada

    Magna (IN)
    …**_Computer_** Knowledge of MS Office package (especially Excel) Knowledge of analysis and engineering tools such as version control/configuration management, UML ... tools, static code check tools Working knowledge of CAN and...CANape, neoVI **About the Role** The Software Architect Team Lead is responsible for leading a team of functional… more
    Magna (05/22/24)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    …ADC etc. + Hands on experience running Spice simulations, EM/IR analysis , and static timing analysis /closure + Experience with spice simulation for noise ... challenging and exciting role in improving the netlist and timing quality of our designs and if you are...of Nvidia's next generation products by performing detailed transistor-level analysis on the design. + Drive the design and… more
    NVIDIA (05/08/24)
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  • Associate Director Electrical Engineer - FPGA…

    RTX Corporation (Cedar Rapids, IA)
    …and timing constraints. + Perform device synthesis, place and route. + Perform static timing analysis , linting analysis , and clock-domain-crossing ... and Image processing devices to meet system's requirements. + Recommend and lead functional strategies to advance the Complex Hardware discipline and products. +… more
    RTX Corporation (04/11/24)
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