- Qualcomm (Santa Clara, CA)
- …ASIC Design Verification Engineer with strong CPU, ASIC design and verification fundamentals to work in Qualcomm's Global SOC team. This position offers ... for the future. **The JOB** + As a member of the Global SOC Lower Power verification team, you will be responsible for verifying the ASIC low power design,… more
- Meta (Sunnyvale, CA)
- …from transistors, through architecture, to firmware, and algorithms.We are seeking an SoC Modeling ASIC Engineer to support C++/Python modeling and software ... and mapping software pipelines to the dedicated hardware accelerators. **Required Skills:** SoC Modeling ASIC Engineer Responsibilities: 1. Analyze the software… more
- SpaceX (Sunnyvale, CA)
- SOC /ASIC Synthesis & Front-End STA Engineer ...with power intent and upf development for block and SOC top + Familiar with formal verification ... the ultimate goal of enabling human life on Mars. SOC /ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON...IPs into RTL + Develop/modify/run RTL logic synthesis, formal verification , power intent verification and post synthesis… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking to hire a senior verification architect to design verification methodology for our next generation SOCs with AI capabilities for ... and next generation SoCs. + Design and implement new verification methodology solutions, including TB architecture, test...engineer with a real passion for improving design verification efficiency and pushing barriers? If so, we want… more
- Amazon (Sunnyvale, CA)
- …STA) into SoC timing signoff flow. - Work for Systems and Architecture, SoC Integration, Verification , DFT, Mixed Signal, IP owners, Synthesis, Place & Route ... Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our...& Responsibilities: - Includes definition and development of signoff methodology and corresponding implementation solution - Flow for STA,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …place&route and signoff) and/or experience with functional and formal verification tools/ methodology , VIP. Understanding of semiconductor manufacturing ... technology requirements in the digital , custom and function verification space, coordination of sales strategies and efforts across...in sales and account management or as a Applications Engineer or Design Engineer with proven track… more
- Meta (Redmond, WA)
- …in support of our industry leading virtual and augmented reality systems.As a Design Verification Engineer (DVEs), you will be a key contributor in planning, ... industry leading virtual and augmented reality systems. **Required Skills:** Design Verification Engineer Responsibilities: 1. Self sufficient and detail… more
- ManpowerGroup (Austin, TX)
- Our client, is seeking a Emulation Methodology Engineer to join their team. As a Emulation Methodology Engineer , you will be part of the department ... supporting team **Job Title: Emulation Methodology Engineer ** **Location: Austin, TX** **What's the...+ Bring up and debug PCIe, DDR, and generic SOC interfaces. + Integrate and bring up third-party accelerated… more
- NVIDIA (Hillsboro, OR)
- We are now looking for a CPU Design Methodology Engineer : The complexity of chip development has greatly increased over the years. We are now packing tens of ... NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design...and problem-solving skills + Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design… more
- NVIDIA (Santa Clara, CA)
- …how you can make a lasting impact on the world. We seek an RTL Analysis Methodology Engineer to join our Logic Design Implementation team. The team develops and ... supports static RTL verification methodologies for RTL Lint and Logical Equivalence. As...limits of technology and performance for GPU, CPU and SoC markets. What you'll be doing: + Evaluate new… more
- Microsoft Corporation (Mountain View, CA)
- …in an extremely efficient manner. We are looking for a **Principal Design Verification Engineer ** to work in the dynamic Microsoft Artificial Intelligence System ... with 3 rd party IP vendors. + Experience with IP/ SOC verification for a full product cycle... and debug principles, test benches, System Verilog, Universal Verification Methodology (UVM) and C based test… more
- Meta (Austin, TX)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- Meta (Austin, TX)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement block/IP/ SoC verification … more
- Meta (Austin, TX)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- Microsoft Corporation (Raleigh, NC)
- …and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM). + Analyse and debug test failures ... coverage for stimulus and corner cases. + Develop, audit & execute the IP/Subsystem SoC level verification plan. + Close coverage to plug verification … more
- Microsoft Corporation (Mountain View, CA)
- …clients, and augmented reality. We are looking for a **Senior Design Verification Engineer ** to work on leading-edge Intellectual Property (IP) development ... and assertions to verify design correctness. + Develop Universal Verification Methodology (UVM) components to interface between...of experience in design verification with full verification cycle on complex System On Chip ( SOC… more
- Qualcomm (San Diego, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, ... for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model… more
- Meta (Austin, TX)
- …development cycles 12. 5. Verilog, SystemVerilog, C/C++ based verification and UVM methodology 13. 6. IP/sub-system or SoC level verification based on ... Job" online on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Develop functional... test plan. 2. Duties include: Define and implement IP/ SoC verification plans, build verification … more
- IBM (Research Triangle Park, NC)
- …to India for this opportunity. Relocation assistance will be provided. As a Functional verification engineer , you will be working on IBM server processors/ SOC ... like PCIE/CXL, DDR, Flash, Ethernet etc + AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric ...domain crossing verification + Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ + Knowledge… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Verification Engineer for our Tegra group! NVIDIA is seeking outstanding Senior Verification Engineers to verify the design ... writing UVM testbench from scratch and applying constraint random methodology in UVM test environment. + Highly proficient in...Stand Out From The Crowd: + UVM knowledge and SOC verification experience. + Ambitious and highly… more