- SpaceX (Sunnyvale, CA)
- SOC/ASIC Synthesis & Front-End STA Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... with the ultimate goal of enabling human life on Mars. SOC/ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- Qualcomm (Santa Clara, CA)
- …help create a smarter, connected future for all. As a Qualcomm Hardware Engineer , you will plan, design, optimize, verify, and test electronic systems. Qualcomm ... for the development of SoC designs. Roles/Responsibilities: Job responsibilities include RTL Synthesis using state of the art Physical Synthesis Tools; Timing… more
- Amazon (Sunnyvale, CA)
- …is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of ... development of signoff methodology and corresponding implementation solution - Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. -… more
- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/Test) handling, block and top level static timing ... top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level. * Experience in Power Analysis and… more
- Cadence Design Systems, Inc. (Cary, NC)
- …to make an impact on the world of technology. Principal Physical Design Engineer (PNR/Physical Verification/ STA /EMIR) The candidate will have the opportunity to ... planning, power grid design, place and route, clock tree synthesis , timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR… more
- Micron Technology, Inc. (Minneapolis, MN)
- …groundbreaking technology while rapidly growing your abilities. As our Staff ASIC Digital Synthesis Engineer role, you will contribute to the development of ... **In our hybrid role** , you will develop and operate front-end Synthesis flows, including STA , constraint management, Lint/CDC/RDC, front-end/back-end netlist… more
- NVIDIA (Santa Clara, CA)
- …methodologies + Build flows for methodologies incorporating logic/physical synthesis , design planning, equivalence checking for industry-leading chip designs ... , Tcl, C/C++ + Knowledge or experience with logic synthesis , physical design, formal equivalence checking. + Proven track...ASIC methodologies such as RTL Lint, CDC, DFT or STA . + Experience with compute farm interaction: software deployment,… more
- Meta (Austin, TX)
- …(SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/Physical Synthesis using advanced ... corresponding reset sequence for RDC. 8. Develop Timing Constraints for RTL- Synthesis and PrimeTime- STA for the blocks and the top-level including SOC. Analyze… more
- Microsoft Corporation (Santa Clara, CA)
- …or related field. + 7+ years of physical design experience, including hands-on experience in synthesis , place & route, and STA . + 4+ years of experience with ... We are looking for a **Physical Design Methodology Engineer ** . As part of our DPU silicon...Qualifications:** + 10+ years of physical design experience (including synthesis , place & route, LEC, STA , physical… more
- Actalent (Phoenix, AZ)
- …and work with the Designers to create waivers. + Develop Timing Constraints for RTL- Synthesis and PrimeTime- STA for the blocks and the top-level including SOC. ... Position: Silicon Physical Design Engineer III Location: 100% Remote Pay rate: $80-100/hour...and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis , STA , Power). + Work closely with… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... frontend and backend implementation from RTL to gds2, including synthesis , equivalence checking, floor-planning, timing constraints, timing and power convergence,… more
- NVIDIA (Santa Clara, CA)
- …are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are looking for a ... with 6+ years experience in Physical Design + Expertise in physical synthesis and deep understanding of RTL/logic and equivalence checking to achieve better… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in raising ... generation of CPU, GPU or SOC designs. + Owning STA of large subsystems and full chip designs or...or at block-level with additional responsibilities for block level synthesis /optimization + You will be responsible for all aspects… more
- Meta (Sunnyvale, CA)
- …"Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... reset sequence for RDC. 10. Develop timing constraints for RTL- synthesis and PrimeTime- STA for blocks and top-level including SOC. 11. Analyze inter-block… more
- Cadence Design Systems, Inc. (Austin, TX)
- …impact on the world of technology. The primary focus of Senior Principal Solutions Engineer is to support the adoption of Cadence Products to help Chip Designer ... their Design PPA Goals. AE's are expected to possess Synthesis (logical and physical), Place and Route (primary focus...and physical), Place and Route (primary focus ) , STA / SDC skills and some experience supporting tapeouts… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …gate level simulations to verify functionality. + Perform and help debug Synthesis / STA scripts/constraints. + Participate in development of Application notes, ... IP. + Verilog RTL design and gate level verification experience. + Synthesis and STA experience, back-end experience is a plus + Familiarity with industry… more
- Cadence Design Systems, Inc. (Austin, TX)
- …customers in the areas of Digital Design Implementation & Signoff including Synthesis , Place and Route, Design Closure, and timing/power signoff + Guide customers ... (Innovus, ICC2, Fusion Compiler) + Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler) + Experience with...tools in the IC digital implementation & signoff flows ( STA tools) + Strong STA and SDC… more
- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human inventiveness and intelligence. Are you a software engineer with a passion for hardware, ASIC design and VLSI? Be part of a ... methodology! We're responsible for NVIDIA's front-end ASIC software including RTL synthesis , equivalence checking, and early physical design and methodology for all… more
- SpaceX (Redmond, WA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Redmond, WA SpaceX was founded under the belief that a future where humanity is out exploring ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- Micron Technology, Inc. (Atlanta, GA)
- …levels. + Deep knowledge of IP and SoC design flows and methodologies (CDC, Synthesis / STA , Power) + Experience in designing digital or analog circuits using CMOS ... world uses information to enrich life. As a Design Engineer at Micron Technology, Inc., you will be responsible...in ASIC timing constraints generation and timing closure using STA tools (Primetime) and the associated design flow. +… more