- NVIDIA (Santa Clara, CA)
- …our team with varied strengths today! What you will be doing: + Developing physical design methodologies for implementation of graphics processors and SOCs. + ... includes developing unique and creative solutions to the state of the art physical design problems that are needed for NVIDIA chips. + Participate in developing… more
- Google (Sunnyvale, CA)
- …tool workflows in semiconductor environments. + Experience developing and supporting ASIC physical design flows and methodologies in process nodes. + Experience ... trends. + Expertise in one or more aspects of physical design implemenation, including 2.5D and 3DIC...that power all of Google's services. As a Hardware Engineer , you design and build the systems… more
- Google (Mountain View, CA)
- …(ie, Python, Bash, Tcl) for workflow automation and data visualization. + Experience with physical design flow development and design closure for multiple ... and networking technologies that power all of Google's services. As a Hardware Engineer , you design and build the systems that are the heart of the world's… more
- Microsoft Corporation (Mountain View, CA)
- …servers, clients, and augmented reality. We are looking for a Principal Front End Design Methodology Engineer to work in the dynamic Microsoft Artificial ... on Chip (AISoC) Silicon team. As the Front End Methodology Engineer , you will be responsible for..., verification, design for testing( DFT) and physical design to ensure quality, performance and… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are a ... (or equivalent experience) + 8+ years of experience in logic design implementation and/or physical design implementation + Deep understanding of logic… more
- NVIDIA (Santa Clara, CA)
- …today. The NVIDIA Clocks group is looking for a top ASIC Methodology engineer with proven experience in high-speed logic design and verification. In order to ... needs to balance high frequency clocks with power, DFT, noise, circuit and physical design constraints. What you'll be doing: + Develop Clock RTL generation and… more
- Qualcomm (Santa Clara, CA)
- …Engineering Group > ASICS Engineering **General Summary:** We are looking for an ASIC Design Verification Engineer with strong CPU, ASIC design and ... team, you will be responsible for verifying the ASIC low power design , architecture and micro-architecture of by applying advanced low power verification… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part ... inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and...experience to improve the convergence flows working with the Methodology Team. What we need to see: + BS… more
- Qualcomm (Santa Clara, CA)
- …**Job Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** A SOC Physical Design Engineer plays a crucial role in the ... products at Qualcomm. This role requires strong knowledge of physical design tools (like Cadence or Synopsys),...and cross-functional teams to achieve project goals and resolve design challenges. * Methodology Development: Participating in… more
- Qualcomm (Santa Clara, CA)
- …create designs that push the envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer , you will build and support the ... flows, and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are ... work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and low-power designs + Focus… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital ... Primetime. + Working closely with R&D on tools and methodology improvements + Create and contribute technical content for...+ Bachelor's degree with at least 3-6 years of design /EDA experience or Master's degree with at least 4… more
- Actalent (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. About ... Description: Run Logic/ Physical Synthesis and generate optimized Gate Level Netlist...PTPX must have. + Experience with RTL Synthesis and design optimization for Power Performance Area. + Experience with… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …with customers doing challenging designs at advanced nodes and help them with design implementation and signoff. Will serve as the technical expert on Cadence tools ... as well as a valued consultant on design and implementation issues. Will script up solutions or...required; 3-5 years of experience in Power Signoff and Physical Implementation of designs at 20nm and below, on… more
- Skyworks (San Jose, CA)
- Sr. RFIC Design Engineer Apply now " Date:May 16, 2024 Location: San Jose, CA, US Company: Skyworks If you are looking for a challenging and exciting career in ... of world-class products, and see your valuable inputs directly translate into improved design methodology , business culture, and work environment. Join us to… more
- Microsoft Corporation (Mountain View, CA)
- …cloud servers, clients, and augmented reality. We are looking for a **Senior Design Verification Engineer ** to work on leading-edge Intellectual Property (IP) ... constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness. + Develop Universal Verification Methodology (UVM) components… more
- Qualcomm (Santa Clara, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, from ... power IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development and… more
- Amazon (Sunnyvale, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. ... & Responsibilities: - Includes definition and development of signoff methodology and corresponding implementation solution - Flow for STA,...- Should be able to work closely with IP Design teams and Backend Physical Design… more
- Meta (Sunnyvale, CA)
- …or power methodology development 12. 5. Logic synthesis and optimization 13. 6. Physical Design (ECO) and 14. 7. Hardware/ASIC lab debug and bring up. ... "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Work on architecture exploration and micro-architecture… more
- Qualcomm (Santa Clara, CA)
- …correlation. + Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis ... team you will be working on WiFi (802.11x) technology, SOC Design , Low Power micro-architecture, Power Intent/Implementation, power estimates and power reduction… more